| PART |
Description |
Maker |
| 74F109 I74F109D I74F109N N74F109D N74F109N 74F109_ |
Positive J-K positive edge-triggered flip-flops F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
From old datasheet system
Positive J-Knot positive edge-triggered flip-flops
|
NXP Semiconductors N.V.
PHILIPS[Philips Semiconductors]
|
| 74ALS109AN 74ALS109A 74ALS109AD |
Dual J-K positive edge-triggered flip-flop with set and reset ALS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
|
Rochester Electronics, LLC
PHILIPS[Philips Semiconductors]
NXP Semiconductors
|
| 74LVC1G74GD125 |
Single D-type flip-flop with set and reset; positive edge trigger; Package: SOT996-2 (XSON8U); Container: Reel Pack, Reverse, Reverse LVC/LCX/Z SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
|
NXP Semiconductors N.V.
|
| DM74ALS109A DM74ALS109AN DM74ALS109AM DM74ALS109AM |
From old datasheet system
ALS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
ALS SERIES, DUAL POSITIVE EDGE TRIGGERED J-KBAR FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP16
Dual J-K Positive-Edge-Triggered Flip-Flop with Preset and Clear(???杈圭?瑙????-K瑙?????甯??缃??娓??绔?伎
|
FAIRCHILD[Fairchild Semiconductor]
Fairchild Semiconductor Corporation
|
| 74V1G80 |
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
|
ST Microelectronics
|
| 74V1T80STR 74V1T80 74V1T80CTR |
SINGLE POSITIVE EDGE TRIGGERED D-TYPE FLIP-FLOP
|
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| M27W201-80K6TR M27W201-200NZ6TR M27W201-80NZ6TR M2 |
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
Test Spring Probe; Current Rating:3A; Leaded Process Compatible:Yes; Length:0.060"; Peak Reflow Compatible (260 C):No; Tip/Nozzle Style:90 Concave RoHS Compliant: Yes 2兆位56Kb × 8低压紫外线可擦写可编程只读存储器和OTP存储
Triple 3-Input Positive-AND Gates 14-SO 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SO 0 to 70
Triple 3-Input Positive-AND Gates 14-PDIP 0 to 70
Triple 3-Input Positive-AND Gates 14-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-SOIC 0 to 70
Dual J-K Positive-Edge-Triggered Flip-Flops With Clear And Preset 16-PDIP 0 to 70
2 Mbit 256Kb x 8 Low Voltage UV EPROM and OTP EPROM
2 MBIT (256KB X8) LOW VOLTAGE OTP EPROM
|
STMicroelectronics N.V.
意法半导
STMICROELECTRONICS[STMicroelectronics]
ST Microelectronics
|
| SN74AUP1G80DBV SN74AUP1G80DBVRG4 |
<font color=red>[Old version datasheet]</font> Low-Power Single Positive-Edge-Triggered D-Type Flip-Flop
|
TI store
|
| SN74LVC2G74DCT3 SN74LVC2G74DCTRE6 SN74LVC2G74DCTRG |
<font color=red>[Old version datasheet]</font> Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset
|
TI store
|
| 74AUP2G79GF 74AUP2G79GS |
Low-power dual D-type flip-flop; positive-edge trigger AUP/ULP/V SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO8
|
NXP Semiconductors N.V.
|
| MC100EL51DG MC100EL51DR2G MC100EL51DT MC100EL51DTG |
5V ECL Differential Clock D Flip-Flop 10EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, DSO8
5V ECL Differential Clock D Flip-Flop 10EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
5V ECL Differential Clock D Flip-Flop; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Rail; Qty per Container: 98 10EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8
5V ECL Differential Clock D Flip-Flop(5V ECL 差分时钟D触发
|
ONSEMI[ON Semiconductor]
|
